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IMP2 1 1 9
DATA COMMUNICATIONS
9-Line ULTRA3 LVD/SE SCSI Terminator
The IMP2119 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10 standards committee for low voltage differential (LVD) termination. Multimode compatibility permits the use of legacy devices on the bus without hardware alterations. Automatic mode selection is achieved through voltage detection on the diffsense line. The IMP2119 delivers the ultimate in SCSI bus performance while saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The individual high bandwidth drivers also maximize channel separation and reduce channel to channel noise and cross talk. The high bandwidth architecture insures ULTRA3 performance. When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. In application, this pin is tied to the DIFFSENSE input of the corresponding LVD transceivers. This action enables the LVD transceiver function. DIFFSENSE is capable of supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places the IMP2119 in a high impedance state indicating the presence of an HVD device. Tying the pin LOW places the part in a single-ended mode while also signaling the multimode transceiver to operate in a singleended mode. Recognizing the needs of portable and configurable peripherals, the IMP2119 have a TTL compatible sleep/disable mode. During this sleep/disable mode, power dissipation is reduced to a meager 15A while also placing all outputs in a high impedance state. Also during
Key Features
N N N N N N N N N N N N Auto-selectable LVD or single-ended termination 3.0pF maximum disabled output capacitance Fast response, no external capacitors required Compatible with active negation drivers 15A supply current in disconnect mode Logic command disconnects all termination lines DIFFSENSE line driver Ground driver integrated for single-ended operation Current limit and thermal protection Hot-swap compatible (single-ended) Compatible with SCSI, SPI-2, SPI-3, SPI-4 ULTRA160 and ULTRA320 Pin compatible with DS2119
sleep/disable mode, the DIFFSENSE function is disabled and is placed in a high impedance state.
Another key feature of the IMP2119 is the master/slave function. Driving this pin HIGH or floating the pin enables the 1.3V DIFFSENSE reference. Driving the pin LOW disables the on board DIFFSENSE reference and enables use of an external master reference device.
Block Diagram
TPWR ISO Internal VREF 1.30V Power ON SE 2.2V 1.07mA LVD 1.25V M/S 10mA 1.07mA Window Comp. 20k DIFF_CAP Power ON (c) 2002 IMP, Inc. MODE Control & Delay SE HVD LVD Power ON & MODE Delay
5241/42 01 eps
SE 2.85V, 22.5mA
1 of 9
200
52.5 52.5
SE DISC/HVD LVD
LVD(-) / SE SE HVD 20 LVD LVD(+) / SE (Pseudo-GND)
Latch SE HVD LVD
DIFFSENSE
Data Communications
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IMP2 1 1 9
Pin Configuration
TSSOP-28
NC R1P R1N R2P R2N HS GND R3P R3N R4P R4N R5P 1 2 3 4 5 6 7 8 9 10 11 IMP2119 28 TPWR 27 NC 26 R 9 N 25 R9P 24 R 8 N 23 R8P 22 HS GND 21 R7N 20 R7P 19 R 6 N 18 R6P 17 DIFF_CAP 16 DIFFSENSE 15 MASTER/SLAVE
R 5 N 12 ISO 13
GND 14
PW Package
Ordering Information
Part Number
IMP2119CPW
Temperature Range
0C to 70C
Package
28-pin Plastic TSSOP
5241/42_t02.eps
Note:
For Tape and Reel, append the letter "T" to part number. (i.e. IMP2119CPW/T)
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V Operating Junction Temperature Plastic (DB, PW Packages) . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . . -65C to 150C Lead Temperature (Soldering, 10 sec.) . . . . . . 300C Note:
1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
Thermal Data
PW Package: Thermal Resistance Junction-to-Ambient, JA . . . . . . 100C/W Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. No ambient airflow is assumed.
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IMP2 1 1 9
Pin Description
Pin Name
R(1,2,3,4,5,6,7,8)N , R(1,2,3,4,5,6,7,8)P TPWR
Function
Negative signal termination lines for LVD mode. Signal termination lines for SE mode. Positive signal termination lines for LVD mode. Pseudo-ground lines for SE mod e. Power supply pin for terminator. Connect to SCSI bus TermPwr. Must be decoupled by one 4.7F low-ESR capacitor for every three terminator devices. It is absolutely necessary to connect this pin to the decoupling capacitor through a very low impedance (big traces on PCB). Keeping distances very short from the decoupling capacitors to the TPWR pin is also critical. The value of the decoupling capacitor is somewhat layout dependant and some applications may benefit from an additional 0.1F decoupling capacitor at the TPWR pin. Enables / disables terminator. See Table 2 for logic lev els Terminator ground pin. Connect to gro.und Sometimes referred to as M/S pin. Used to select which terminator is the controlling device. MASTER/SLAVE pin HIGH or Open enables the DIFFSENSE output drive. See Table 1. This is a dual function pin. It drives the SCSI bus DIFFSENS line. It is also the sense pin to detect the SCSI bus mode (LVD, SE or HVD). DIFFSENSE output drive can be disabled with a LOW level on the MASTER/SLAVE pin. See Table 1 and Table 2. Internally connected to DIFF _CAP pin trough 20Kohms resistor. Internally connected to DIFFSENSE pin through 20k resistor. It can be used as a mode sense pin when the device is a non-controlling terminator (MASTER/SLAVE pin is LOW). An RC filter (20k / 0.1F) is not required on the IMP2119 , as it has an internal timer. No Connect. Pins should be left open.
IS O GND MASTER / SLAVE D IFFSENSE
DIFF_CAP
N.C.
(c) 2002 IMP, Inc.
Data Communications
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IMP2 1 1 9
Recommended Operating Conditions2
Parameter
TermPwr Voltage LVD SE Signal Line Voltage Disconnect Input Voltage Operating Virtual Junction Temperature Range
Symbol
VTERM
Min
3.0 3.5 0 0 0
Typ
Max
5.25 5.25 5.0 VTERM 70
Units
V
V V C
5241/42_t03.eps
Note:
2. Range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0C TA 70C. TermPwr = 4.75V. ISO : IMP2119 = LOW. Low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature.
Parameter
LVD Terminator Section TermPwr Supply Current Common Mode Voltage Offset Voltage Differential Terminator Impedance Common Mode Impedance Output Capacitance Output Leakage
Symbol Condition
LVD ICC VCM VFSB ZD ZCM CO ILEAK All terminator lines = Open ISO> 2.0 V Open circuit between - and + (see Note 3) VOUT differential = -1V to 1V 0V to 2.5V ISO > 2.0 V .0 ISO > 2.0V VLINE = 0V to 4V, TA = 25C ISO > 2.0 V TPWR = 0V, V LINE = 2.7V DIFFSENSE = 1.4V to 0V
Min Typ Max Units
25 1 1.25 11 2 105 200 2.5 30 35 1.375 125 110 300 2 1 115 1.2 5.0 1. 3 1.4 15.0 200 10 ms V mA A A mA A V mV pF A
1.125 100 100 100
Mode Change Delay DIFFSENSE Section DIFFSENSE Output Voltage DIFFSENSE Output Source Current DIFFSENSE Sink Current DIFFSENSE Output Leakage Single-Ended Terminator Section TermPwr Supply Current
tDF VDIFF IDIFF
VDIFF = 0V ISINK (DIFF) VDIFF = 2.75V ISO > 2.0V ILEAK (DIFF) TA = 25C SE ICC All terminator lines = Open, MASTER/SLAVE = 0V All terminator lines = 0.2V, MASTER/SLAVE = 0V DISCONNECT > 2.0V VOUT = 0.2V VOUT = 4V, all lines ISO > 2.0V ISO > 2.0V VOUT = 0V to 4V, TA = 25C ISO > 2.0 V TPWR = 0V, LINE = 2.7V, TA = 25C I = 1mA
Terminator Output High Voltage Output Current Sink Current Output Capacitance Leakage Current
VO IO ISINK CO ILEAK
2.6 21 45
7 214 15 2.85 23 65 2. 5
10 226 35 24
mA A V mA mA pF A
2 I 100 150
Ground Driver Impedance Thermal Shutdown Note: 3. Open circuit fallsafe voltage.
ZG
C
4
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(c) 2002 IMP, Inc.
IMP2 1 1 9
Electrical Characteristics
Parameter
ISO Section ISO Thresholds Input Current MASTER/SLAVE Section MASTER/SLAVE Thresholds Input Current VTH (MS) IIL (MS) IIL (MS) MASTER/SLAVE = 0V MASTER/SLAVE = 2.4V 100 0.8 2.0 10 V A nA
5241/42_t05.at3
Symbol Condition
VTH IIL IIH ISO = 0 V ISO = 2.4V
Min Typ Max Units
0.8 10 0 2.0 10 V A nA
(c) 2002 IMP, Inc.
Data Communications
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IMP2 1 1 9
Application Information
VOD = V(-) - V(+), Logic = 0 V(+) 100mV
VCM
NEGATED
0V V(-) -100mV
5241/42_04.eps
5241/42_05.eps
Figure 1. Bus Voltage
Figure 2. VOD
-
- +
IMP2119
+
IMP2119
5241/42_06.eps
Figure 3.
Table 1. MASTER/SLAVE Function Table
MASTER/SLAVE
L* H Open (Pull-up)
DIFFSENSE Status
HiZ 1.3V 1.3V
Output Current
0mA 15mA Source 15mA Source
5241/42_t06.at3
* When in the LOW state, the terminator will detect the DIFFSENSE line state.
Table 2. DIFFSENSE/Power Up/Power Down Function Table
IMP2119 DISCONNECT
L L L H Open
Outputs DIFFSENSE
L < 0.5V 0.7V to 1.9V H > 2.4V X X
Status
Enable Enable Disable Disable Disable
Type
SE LVD Hi Z Hi Z Hi Z
Current
7mA 21mA 1mA 10A 10A
5241/42_t07.eps
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IMP2 1 1 9
Application Information
HOST
TPWR TPWR 1- 1+ Data Lines (9) 9- 9+ DIFFSENSE ISO ISO M/S GND NC* DIFF_CAP* + Pin 1 4.7F* 0.1F 20k 20k 9- 9+ DIFFSENSE ISO M/S GND DIFF_CAP* NC* + Pin 1 0.1F 4.7F* ISO 1- 1+
PERIPHERAL
TPWR TPWR
IMP2119
IMP2119
+
+
TPWR
1- 1+ Data Lines (9) 9- 9+
1- 1+
TPWR
+
4.7F
+ IMP2119
4.7F
IMP2119
9- 9+ DIFFSENSE ISO M/S GND DIFF_CAP* NC* + Pin 1 4.7F*
DIFFSENSE ISO M/S GND NC* DIFF_CAP* Pin 1
+
4.7F*
TPWR
1- 1+ Data Lines (9) 9- 9+
1- 1+
TPWR
IMP2119
IMP2119
9- 9+ DIFFSENSE ISO M/S GND DIFF_CAP* NC* + Pin 1 4.7F*
DIFFSENSE ISO M/S GND NC* DIFF_CAP* + Pin 1 4.7F*
* The capacitor on pin 1 can be placed on the IMP2119CPW. This capacitor is not required with IMP devices.
Figure 5. Suggested IMP2119 Universal Application Schematic
(c) 2002 IMP, Inc.
Data Communications
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IMP2 1 1 9
Package Dimensions PW
Thin Small Shrink Outline (TSSOP) (28-Pin)
Inches Min Max Millimeters Min
0.80 0.19 0.09 9.60 4.30 0.65 BSC 0.05 - 0.45 0 6.25 - 0.15 1.20 0.75 8 6.50 0.10
Max
1.05 0.30 0.20 9.80 4.5
Thin Small Shrink Outline (TSSOP) (28-Pin)
A .032 .041 B 0.007 0.012 C 0.0035 0.0079 D 0.378 0.386 E 0.169 0.176 F 0.025 BSC G 0.002 0.005 H - 0.047 L 0.017 0.030 M 0 8 P 0.246 0.256 *LC - 0.004 * Lead Coplanarity.
E
P
123
D F AH SEATING PLANE B G L
E
M C
24-Pin (TSSOP).eps
5241/42_t01.eps
8
408-432-9100/www.impweb.com
(c) 2002 IMP, Inc.
IMP2 1 1 9
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Fax: 408-434-1085 e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 2002 IMP, Inc. Printed in USA Publication #: 7001 Revision: C Issue Date: 11/01/01 Type: Product

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